Tracking Status Detector for a digital Delay Lock Loop.

摘要

The patent application describes an unlocked detector for a digital delay lock loop which employs an up-down counter that periodically accumulates the algebraic sum of the quantized positive and negative adjustments made at a preselected rate by the incremental phase modulator. Whenever this sum reaches a specified threshold value corresponding to a particular phase error, an unlocked indication is given. Arrangements utilizing the same principle are disclosed for analog loops.