Design of Chip Architectures for Accurate Inner Product Computation

摘要

A set of architectures is introduced, capable of exact computation of thefloating point inner product. An inner product is the sum of products. To compute an inner product exactly, no rounding errors may be made at the computation of the product terms as well as the intermediate sum. The floating point numbers are elements of a finite set, and therefore, the product terms are also elements of a finite set. These product terms may be summed, without loss of precision to an intermediate sum and stored in an accumulator, which, though large, is finite. The performance of the architectures is analyzed. The actual implementation of the heart of the chip is presented. A flexible cell generator is introduced. Conclusions and suggestions for further work are given.