Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 Volts

摘要

A comparison of single event upset and latchup test results for devices operated at several bias levels, from 2.5 V to 6 V, is reported. Vulnerability to SEU increased with decreasing bias, whereas the opposite pattern was observed for SEL. The relationship between threshold SEU vulnerability and bias is not regular, which precludes the use of simple prediction schemes for obtaining the expected vulnerability at 3.3 V from existing 5 V data.