Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings

摘要

This paper discusses several possible uses of the knowledge of how user's logical designs are mapped to physical FPGA circuits. Some of these uses include power analysis, useful feedback on physical design implementations, and direct, quick modifications of physical designs. As an example of how this knowledge can be used, we describe, in detail, how to determine the logical-to- physical mapping of Xilinx XC4000 circuits created with JHDL and how this mapping and FPGA state sampling, or readback, neables us to provide a hardware debugging environment with a complete visiblit of all flip-flops and LUT RAMs in executing hardware.