1K x 1K and Larger Staring Focal Plane Arrays.

摘要

Until recently, very large focal plane arrays (> 1K x 1K pixels) could only be fabricated using low density > 2 micrometer CMOS processes employing full wafer projection lithography. Higher density processes use steppers to expose the patterns on the wafer which have limited the die size to the area able to be exposed in a single step. This placed an upper limit on the readout die size of about 18-22 mm along a side. While stitching techniques have been used to pattern larger die, most silicon foundries are unwilling to accept such projects. Raytheon has recently pioneered a foundry friendly technique that allows an arbitrarily large readout to be fabricated using advanced submicron (0.6 to 0.8 micrometer) and deep submicron (0.25 to 0.35 micrometer) CMOS processes.