High-Speed and Low-Power VLSI Error Control Coders

摘要

This final report describes our research results obtained during the period August 1, 2001 to July 31, 2004 by support from the ARO grant 'High Speed and Low Power VLSI Error Control Coders' ARO Grant Number:DA/DAAD19-01-1- 0705(42436-CI). Research results obtained in the areas of architectures for product turbo coders (based on component codes such as BCH codes, extended Hamming codes, and single parity check codes), space-time block codes, low- density parity check (LDPC) and long BCH codes are described. Efficient implementation of AES cryptosystems are described. Architectures for ultra wideband communication systems are summarized. Erasure decoding in Reed-Solomon codes and some preliminary results on soft-decision Reed-Solomon decoders are outlined.