Leakage Reduction for On-Die Caches

摘要

Technology scaling is associated with exponential increase in leakage for every subsequent technology generation. Since cache memories take up a significant portion of the die in modern processors, leakage contributes largely to power dissipation in caches. Our effort was to reduce leakage in large caches. We investigated several leakage-tolerant co-design techniques at the circuit and architecture levels. We also considered the effectiveness of the proposed techniques with predictive scaled devices. In particular, we determined that source biased and body biased caches can be effective in reducing leakage significantly. A 0.18 micrometers, 1.8 V, 16 KB source-biased static random access memory (SRAM) test chip shows 94.2 percent reduction in SRAM cell leakage at a performance penalty of less than 2 percent. Measured results also indicate that our proposed memory cell improves SRAM static noise margin by 25 percent. It should be noted that our techniques do consider different components of leakage current and process parameter variations.