Collaborative Platform for DFM

摘要

This dissertation addresses the two biggest challenges in Design for Manufacturing (DFM), how to inject process variations into design and how to identify and quantitatively characterize the main sources of transistor performance variation so that the information that is fed into design is accurate enough to make design tradeoff decisions effectively. To address these challenges the Collaborative Platform for DFM has been built in three main parts; the Parametric Yield Simulator, which is a scripted link between process simulation, non-rectangular device modeling, and circuit simulation, a process characterization strategy that leverages a large set of process sensitive electrical test structures for extracting process conditions, and a collaborative database that serves as the glue between simulation and experiment and facilitates high volume data analysis. The Parametric Yield Simulator (PYS) is built as a modular platform that links processing, currently lithography simulation, device modeling, and circuit analysis. This simulation flow is built around a non-rectangular transistor model that uses a set of channel position dependent slice lookup tables for fast model generation and translates a 2D geometrical gate shape into an equivalent 1D compact transistor model. The PYS can be wrapped with perl scripts to simulate layouts across the lithographic process window and hence be used for rapid prototyping of process sensitive test structures.