Variable Swing Optimal Parallel Links - Minimal Power, Maximal Density for Parallel Links

摘要

The rapid growth of chip-to-chip interconnect density, speed, and the demand for smaller and more portable devices has taken signal integrity engineers to the limits of PCB (Printed Circuit Board) design. Special care has to be taken in the design stage to guarantee that noise specifications are met and power specifications and geometry of the links ensure minimal crosstalk noise in the system. In parallel links, specific parameters of layout geometry are dictated during the design stage to meet noise requirements, generally increasing the space between channels to minimize crosstalk noise. This step determines and fixes the characteristic impedance of the lines and the induced crosstalk among them. Given that design planning is done to ensure that all specifications are met in the worst case scenario, the lack of layout freedom leads to a waste of space in high-speed systems. With the increasing interconnect density, a waste of power and space can no longer be afforded. The work presented in this dissertation provides a novel technique to minimize the crosstalk in parallel links by the use of anti-coupling capacitances between adjacent links using an onboard accelerated Bit Error Rate (BER) testing technique. With this methodology, the channels can be routed as close as possible minimizing the space needed. The methodology automatically optimizes the values of the capacitances so that noise specifications will be met. The designed receiver also allows the algorithm to adjust the termination resistance to minimize the reflections based on accelerated BER measurements. After both optimizations have been done, each differential pair on the parallel link can be treated as a serial link, allowing a per-link power optimization using accelerated BER measurements.