Sensor Network Optimization by Using Error-Correcting Codes.

摘要

The objective of this project is to develop efficient very large scale integrated (VLSI) error-correcting encoders and decoders to be used in sensor network applications. In addition, decoders with adjustable error- correcting capability will be designed so that trade-offs can be made on signal transmission power and receiver power. During this project period, novel schemes were proposed to further increase the speed and reduce the area of the interpolation-based generalized minimum distance (GMD) decoder of Reed-Solomon (RS) codes. In addition, the complexity analysis of the GMD decoder was generalized to take into account different codeword length, code rate and parallel processing factor. A reduced-complexity parallel interpolator has also been developed for the low-complexity Chase (LCC) algebraic soft-decision RS decoding algorithm. Compared to previous designs, it not only has much smaller area, but can run at higher speed. Adopting this design, the overall decoder can achieve substantially higher efficiency. Another achievement of this year is that the LCC decoder has been optimized, so that it can also carry out high- speed hard-decision decoding with negligible hardware overhead.