This paper deals with the problem of realizing a single-element-kind network exhibiting a performance at n properly chosen terminal pairs (n-port).nThe difficulties encountered by various authors who have dealt with such a task arise from the fact that the synthesis of n-ports involves two kinds of problems:na) the topological problem of finding out a network structure, the properties of which agree with the requested performance;nb) the physical problem of deciding whether the latter can be realized on such a structure using neither non-conventional network elements, such as negative resis¬tors, nor ideal transformers.nMany techniques have been proposed for the log¬ical design of combinational circuits constructed of AND gates and OR gates.nSometimes these procedures can be extended to apply to networks of NAND or NOR gates, but the use of these gates often gives rise to problems for which new techniques are required. The problem considered in this paper is one of those in which it is necessary to make reference to specific properties of NAND or NOR gates for the logical design of the minimal network.
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