Synthesis of Logic Functions on an Array of Integrated Circuits

摘要

This report summarizes the results of a study on the utilization of arrays of logic cells to provide any desired switching function. Each logic cell can be connected to other cells in the array by means of simple, preplanned interconnection patterns. The work of the past year has been devoted mainly to the problem of utilizing faulty arrays in an economical manner and to the problem of improving the connectivity in the array by means of increasingly complex patterns. The study of faulty arrays has been divided into three areas: error-correction codes uded to compensate for faulty cells in memory-type arrays; bit-skewing and autonomous register compacting techniques which permit the use of simple wiring patterns on a faulty array; and fault avoidance by means of computer-determined stretching actions on the fault-free wiring pattern which preserve the original wiring topology and do not introduce new crossovers. The notion of a control array superimposed on a logic array is introduced as a method of achieving a programmable array; the control array is used to specify the logic function of each cell and its connectivity in the overall logic array. The study of improved connectivity introduced two interconnection patterns which have been investigated elsewhere for use in telephone switching and in macrocellular arrays, namely Clos three-stage networks and Elspas n(d,k) graphs, respectively. (Author)