Investigation of SOS Processes for Fabrication of Radiation Hardened MIS Devices and Integrated Circuits.

摘要

The program has the objectives of obtaining a better understanding of the radiation-induced n-channel SOS leakage problem and of examining the effects of processing variations on the radiation-induced leakage. Experiments were performed on devices from 6 processing lots--encompassing variations in silicon doping densities and techniques, device design, and device geometry. Experiments on devices having the sapphire thinned to approximately 3 mils and with a gate electrode on the sapphire demonstrated that the radiation-electrode n-channel leakage is due to inversion of the p-type silicon at the sapphire interface by positive charge trapped in the sapphire. This charge was found to saturate at a value of approximately 3 x 10 to the 11th power charges/sq cm, under conditions of +10 V drain bias during irradiation.