Cost and Reliability Aspects of Large CMOS Integrated Circuits for Fuzing Applications.

摘要

A complementary metal-oxide-semiconductor (CMOS) large-scale integrated circuit (LSIC) has been designed for use in the sensor of the XM75 Scatterable Mine. The CMOS digital technology lends itself to this application because of its low current drain and multiple sourcing of vendors. The cost of a CMOS LSIC is a function of the cost per electrically good die, the level of electrical and mechanical testing, and assembly and packaging costs. Circuit yields in terms of relative circuit areas are discussed in the literature according to assumed defect density distributions. Absolute yield data for production IC's have been obtained in personal communications with industry personnel. The stringency of the mechanical and environmental tests required for an IC will affect the final IC cost, since there is yield loss at both the wafer and the packaged device level.