Automated Synthesis of Digital Hardware Modules; Simulation and Verification of Interconnections

摘要

The research described in this final report involves two basic areas: automated design and optimization of digital hardware, and simulation and verification of interconnections between digital system modules. Both of these are part of the CMU-DA (Design Automation) project (formerly called the RT-CAD project). We have investigated strategies for computer-aided optimization of the control part of digital systems hardware by developing a discrete optimization technique and a strategy for applying this technique. In addition, we have developed a design aid for computer interconnection evaluation by simulation techniques. Finally, we have begun to design a system to formally verify that a description of interconnections is functionally correct. (Author)