首页> 外国专利> Debugging Apparatus Using Both Very Large Scaled Digital System Realized in Hardware and Simulation and Debugging Method For Verifying Ultra Large Design

Debugging Apparatus Using Both Very Large Scaled Digital System Realized in Hardware and Simulation and Debugging Method For Verifying Ultra Large Design

机译:使用硬件实现的超大规模数字系统调试设备以及用于验证超大型设计的仿真和调试方法

摘要

PURPOSE: A debugging device and a method are provided to make an application of a design verifying method mixed by an emulation with a simulation of a large-sized digital system possible although a scale of a design verification-objected circuit is exceeded to a limit of the simulation in a design verification for mixing the emulation with the simulation thereof. CONSTITUTION: An extended circuit capable of performing an input/output probe is automatically created by adding a probe additional circuit for an input/output probe to a design verification and a check-objected circuit. An input/output probe interface module(26) connects a hardware board embodied by the extended circuit in a hardware chip to server computers(20), controls a performance of the hardware board, performs an input/output probe with respect to the hardware chip on the hardware board in a specific time or a specific condition, and exchanges performance result information with respect to a design verification and a check-objected entire circuits or a partial circuit between the server computer(20) and the hardware chip rapidly. An emulation and a simulation are performed at least one times automatically alternately using the server computer(20) and a predetermined simulation server computer for simulating the design verification and the check-objected entire circuits or the partial circuit. Thus, an effective debugging is possible.
机译:目的:提供一种调试装置和方法,以使通过仿真与大型数字系统的仿真相混合的设计验证方法的应用成为可能,尽管超出了设计验证对象电路的规模。设计验证中的仿真,以将仿真与仿真混合在一起。构成:能够执行输入/输出探针的扩展电路是通过将用于输入/输出探针的探针附加电路添加到设计验证和检查对象电路中而自动创建的。输入/输出探针接口模块(26)将由硬件芯片中的扩展电路体现的硬件板连接至服务器计算机(20),控制硬件板的性能,针对硬件芯片执行输入/输出探针。在特定时间或特定条件下在硬件板上进行操作,并且在服务器计算机(20)和硬件芯片之间快速地交换关于设计验证和检查对象的整个电路或部分电路的性能结果信息。使用服务器计算机(20)和预定的模拟服务器计算机至少交替地自动至少一次进行仿真和仿真,以仿真设计验证和检查对象的整个电路或部分电路。因此,可以进行有效的调试。

著录项

  • 公开/公告号KR20020069468A

    专利类型

  • 公开/公告日2002-09-04

    原文格式PDF

  • 申请/专利权人 YANG SEI YANG;

    申请/专利号KR20010048417

  • 发明设计人 YANG SEI YANG;

    申请日2001-08-08

  • 分类号G06F11/26;

  • 国家 KR

  • 入库时间 2022-08-22 00:30:28

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