Solid State PFN Clipper Stack Analysis Under High Peak Power Conditions.

摘要

Previously reported results of a pulse forming network (PFN) end-of-line clipper (EOLC) point out that solid-state diode EOLC stacks are deficient in important pulser requirements; namely stack reverse leakage, forward current rate-of-rise, forward recovery and high forward drop. Some of these deficiencies can be reduced through an improved understanding of silicon diode rectifier operation at high pulsed power conditions. The apparent current rate-of- rise limitation for high pulsed currents and the cause of the apparent phase lag under forward biasing is discussed. The relative contributions of lead inductance, effects of diffusion capacitance, minority carrier transit times and charge storage decay times are reported for two commercial EOLC assemblies. Results of pulser evaluation suggest that improvements can be made in the EOLC design and its operation to reduce inverse voltage appearing at the switch under mis-matched (load-PFN) conditions.