Design and Simulation of an Ultra Reliable Fault Tolerant Computing System Voter and Interstage

摘要

The purpose of this thesis was to design a portion of the hardcore for an ultra reliable fault tolerant computing network. The design focused on the interstage, the midvalue voter, and the interface to the CPU. The design also investigated the use of the custom slave processor mode of the National Semiconductor 32016-10 CPU as the interface to the interstage. The primary focus of the design was reliability. Therefore the number of gates used was minimized as much as possible. Finally, the entire design was constructed and tested on the Valid Logic Inc. SCALD system computer aided design (CAD) workstation. Effectiveness of the CAD system for large designs was also studied.