SBNR (Signed Binary Number Representations) Digital Signal Processor Architecture

摘要

The following research was proposed in a three-year period. This constitutes significantly distinct efforts which complement the existing efforts in current adaptive signal processor architecture research. Briefly, these tasks comprised a study of non-conventional number system implementations focusing on VSLI enhancements attributable to redundant number systems. This increased practical knowledge should add impetus to many potential signal processing tasks (target trackers, beamformers, communication, receivers, spread spectrum). Three diverse, yet tightly coupled, research topic were posed, centering on the usage of Signed-Digit (SD) arithmetic to solve mult/acc intensive signal processing tasks (streaming data). Efficient implementations for signed-digit arithmetic were sought for systolic arrays. Connectivity and control were investigated for inherent fault-tolerance. Lastly, multiple-valued logic for the Signed Binary number Representations (SBNR) was studied for both fault-tolerance and array regularity. The dominant and focused application of this research was efficient solutions of specific signal processing algorithms. (Author)