100-MHz Pipelined CMOS Comparator

摘要

This paper describes the design of a Very Large Scale Integrated VLSI-compatible Complementary Metal Oxide Semiconductor CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by mean of a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8 bits, offset cancellation is incorporated in the first sense amplifier. In addition, an input sampling network comprised of only passive devices is used to sample the two analog inputs and cancel their common-mode voltage. The comparator has been integrated in a 2-um CMOS technology and has a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate. Keywords: Reprints, Analog integrated circuits, A/D conversion, Analog CMOS circuits. (RH/AW)