Cache for Multi-Threaded Processors on a Split-Transaction Bus.

摘要

A multi-threaded processor has several sets of registers, and therefore can keep several tasks in a state of being ready to run. This ability to combine several independent instruction streams prevents such a processor from getting systematically blocked upon every cache miss involving a long memory access. Unfortunately, upon a cache miss, conventional caches remain unavailable for further processor requests until the cache miss is completely processed. This of course defeats the purpose of this kind of architecture, since memory accesses performed by the other threads might hit in the cache and therefore succeed. Instead, the processor stays idle. This article describes a cache architecture capable of servicing processor requests even while a memory access is currently being performed. For further efficiency reasons, this cache communicates with the memory via a split transaction bus. These two features increase substantially the amount of state information to be kept along with each cache entry, making the cache automaton and protocol quite complicated. We detail the kind of consistency provided by our cache, along with a proof of its validity. As very little theoretical support exists for this kind of proof, we also present a formalism that we developed in the course of this project, and which is suitable for expressing statements of consistency. (rrh)