Hardware Modeling and Top-Down Design Using VHDL

摘要

As digital designs grow more and more complex, some method of controlling thiscomplexity must be used in order to reduce the number of errors and the time spent on a design. VHDL(Very High Speed Integrated Circuit Hardware Description Language) promises to ease the design and verification of complex digital circuits by encouraging the use of top-down design. This thesis demonstrates how VHDL, combined with a top-down design methodology, enables the designer to specify and verify a digital design faster and with fewer errors. The scoreboard, a section of hardware in the Charles Stark Draper Laboratory's Fault Tolerant Parallel Processor, is used as an example to demonstrate the utility of VHDL. The scoreboard is responsible for message processing within the FTPP and thus has a critical effect on performance. It also represents the most significant risk of any component in the FTPP. The use of VHDL has the potential for ensuring an optimal scoreboard design with minimal errors and an improved design time.