Asynchronous Design for Parallel Processing Architectures

摘要

As the integration of VLSI systems becomes larger and denser, implementing a high-performance parallel architecture using a global clock is becoming more inefficient and difficult to design, primarily due to concerns related to clock skew and data synchronization. To solve this problem, a large system may be broken up into asynchronously communicating processors. Each processor can be either asynchronous or synchronous and therefore execute at a rate best suited for individual tasks. Using such asynchronous communication provides a modular design environment in which processors can be individually optimized to yield prominent performance improvement. However the advantages of asynchronous design do not come without a cost, due to two-way communication and design restrictions necessary to avoid hazards and races. In addition, adopting an asynchronous design style requires new methods for synthesis and verification. This research work addressed these methods to simplify the design methodology for asynchronous processors and improve their performance. To provide similar easy-to-use synthesis tools for the design of asynchronous systems, as are available and widely used in the design of synchronous systems, we have developed CAD tools that allow automated design of synchronous, asynchronous, and mixed synchronous/ asynchronous circuits. Our work can be summarized in three major topics: automated gate-level synthesis of asynchronous circuits, a uniform approach to both synchronous and asynchronous circuit synthesis, and efficient verification.