Self Stressing Test Structure Cells

摘要

This report addresses the work performed to design on chip reliabilityprognostics for purposes of monitoring fielded integrated circuits for degradation due to the failure mechanisms of oxide breakdown, electromigration, and hot carrier degradation. The self stressing test structure cells are self-contained standard cells that include the test structure, stressing, and monitoring circuitry and a boundary scan interface to be used with the IEEE 1149.1 boundary scan Test Access Port. The cells have been designed to work within the limitations of a CMOS integrated circuit, i.e., no additional power levels are needed, the cell area has been kept as small as possible, the cells may be incorporated independently from active circuitry, and cells will not degrade chip lifetime. The self stressing cells have been shown to function by simulation, but further study to correlate cell degradation to integrated circuit degradation is required. jg.