Adaptive ADPLL architecture for MPEG system clock related measurements in variable rate environment

摘要

Measurements such as jitter, frequency offset and drift are very important in the quality of service evaluation in digital video broadcast, especially under varying rate environment. This paper presents an all digital phase locked loop (ADPLL) architecture for either VLSI or low cost FPGA implementation. The operation of proposed ADPLL is based on a frequency synthesizer for a very narrow band frequency (±800 Hz), small frequency step and high central frequency (27 MHz). The proposed solution is designed for the real time measurements, feature a very low intrinsic jitter, and adaptive rate variation. The system description and adaptation method are presented with corresponding hardware implementation. Experimental results in term of jitter analysis and adaptation behavior are detailed and discussed.