A Very Low Power Dissipation Inverter-Based Sigma-Delta Interface ASIC for Microelectromechanical Systems Accelerometer

摘要

A very low power dissipation sigma-delta (ΣΔ) interface ASIC for closed-loop capacitive accelerometer is presented in this paper. A third-order electronic ΣΔ modulator is cascaded with the sensing element to eliminate quantization noise. In order to reduce the power consumption, the front-end circuit blocks work on a much lower frequency than the electronic ΣΔ modulator, and an inverter is used as an operational amplifier in electronic ΣΔ modulator, reducing the power dissipation greatly. The measured results indicate that, the total power dissipation is 2.2 mW from a 3.3 V supply, the inverter-based ΣΔ modulator only consumes 148 μW. The noise floor of the accelerometer is 9 μg/Hz~(1/2) in a closed-loop operation, and the achieved figure of merit (FOM, 10 pW/Hz) is better than the previously reported works.