Simulating the Exposure of ICs to Voltage Surges Caused by Nuclear Explosions

摘要

A uniform strategy is developed for testing discrete semiconductor devices and ICs for voltage-surge hardness, allowing comparison of differing models including ICs of high functional complexity. Performance specifications are defined, justified, and implemented for a voltage-surge simulator intended for electrical-overstress hardness tests of ICs. On this basis, a test bed is designed and built for evaluating the hardness of advanced ICs to voltage-surge effects, whether transient or permanent. A procedure is developed for predicting the electrical-overstress hardness of ICs, which enables one to detect both out-of-tolerance and functional failures during testing. The procedure and the test setup are validated by experiments with specific ICs.