Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry

摘要

Inhomogeneities in the parasitic bipolar transistor triggering during an electrostatic discharge (FSD) event are analyzed in 0.35 μm technology grounded-gate nMOSFET ESD protection devices operating in snapback. The current density during high current stress is studied by monitoring the temperature-induced increase in optical phase shift using a backside infrared laser interferometric technique. The distribution of the current along the gate width and the triggered width are investigated as a function of the applied stress current magnitude and device layout parameters. Below a critical stress current the parasitic bipolar transistor triggers inhomogeneously, first at the corners and then in the central part of the device. Under these conditions the current density in the triggered region of the device is nearly constant. At stresses higher than the critical current the device is homogeneously triggered, exhibiting a linear increase of the current density with the stress current in the device. The experimental results are explained in terms of 3D layout effects and compared to results of 3D electrical device simulation.