Linewidth control effects on MOSFET ESD robustness

摘要

This paper advances state-of-the-art design layout considerations for deep sub-micron (0.25μm) advanced single and stacked MOSFETs by addressing linewidth control effects on MOSFET ESD robustness. Advanced failure analysis tools are used todemonstrate linewidth bias. ESD robustness as a function of gate-to-gate spacings is addressed for the first time.