Investigating Degradation Behaviors Induced by DC and AC Bias-Stress under Light Illumination in InGaZnO Thin-Film Transistors

摘要

This paper investigates the effect of DC and AC bias-stress induced degradation behavior in amorphous InGaZnO thin-film transistors (TFTs) under light illumination. Drain current-gate voltage (I_d-V_q) as well as capacitance-voltage (C-V) measurements are employed to analyze the degradation mechanism. Illuminated DC stress leads to not only a negative parallel shift but also a C-V curve distortion at the off-state. This can be attributed to barrier-lowering near the drain side due to the asymmetrical hole-trapping effect. To further verify the origin of the degradation behavior, AC bias with identical stress voltage is imposed on either the gate terminal or the drain terminal. It is deduced that the hole-trapping phenomenon near the drain side is dominated by the voltage across the gate and drain, and is responsible for the degradation characteristic after stress carried out under light illumination.