A Novel Approach to Implement Radix-8 Booth Encoded Modulo Multiplier using PPA

摘要

Multipliers are not only used in logic implementations like ALU, but also in cryptography purpose. Reducing the bit size of the product that has been generated from multiplication process results to cryptography (encoding using RNS and modulo multiplication). The partial products that are generated in intermediate process have to be added. In order to reduce the computation time parallel prefix adder (PPA) is proposed in this work. Modular function is used for final result in order to encode the data, thus the product obtained is divided by 255 (2~8-1), so that quotient acts as cipher text and remainder will be transmitted as data. During decoding cipher text will be multiplied with 255 and added with transmitted data. Coding has been implemented in VERILOG for multiplying two 8 bit numbers using Xilinx ISE design suite and also in Cadence 180nm technology. Simulation results for Xilinx implementation have been obtained using ISIM simulator.