首页> 外国专利> Method of testing a modified booth multiplier, modified booth multiplier suitable for testing by means of this method, and integrated circuit comprising such a modified booth multiplier

Method of testing a modified booth multiplier, modified booth multiplier suitable for testing by means of this method, and integrated circuit comprising such a modified booth multiplier

机译:测试修改后的展位乘法器的方法,适用于通过该方法进行测试的修改后的展位乘法器以及包括这种修改后的展位乘法器的集成电路

摘要

A modified Booth multiplier for multiplying an m-bit number X by an n- bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which overlap by 1 bit into a series Y' of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y' and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent components and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values. Test patterns are generated for establishing static as well as dynamic errors in the combination formed by the Booth encoder and the multiplex circuit and also test patterns which are formed by specific partial products in order to establish static errors in the matrix configuration. In practice the modified Booth multiplier is usually constructed as a multiplier accumulator; in that case test patterns formed by partial products are also used for establishing static errors in the accumulator section.
机译:一种用于将m位数字X乘以n位数字Y的改进的布斯乘法器,包括布斯编码器,该布斯编码器用于将以1位重叠的3位为一组的数字Y转换为数量等于的系列Y'还提供了一种用于从数字X和所述系列Y′形成部分乘积的多路复用电路,以及用于将部分乘积相加在增量位置的全加法器的矩阵配置。这样设计的目的是,可以通过应用特定的X,Y值序列后在Booth乘法器中生成的极少数测试模式来测试修改后的Booth乘法器的组成组件和操作。生成测试图形以建立由布斯编码器和多路复用电路形成的组合中的静态和动态误差,以及生成测试图形,这些图形由特定的部分乘积形成,以便在矩阵配置中建立静态误差。实际上,修改后的Booth乘法器通常被构造为乘法器累加器。在这种情况下,由部分乘积形成的测试图案也可用于在累加器部分建立静态误差。

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