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首页> 外文期刊>International Journal of Electrical Engineering: Transactions of the Chinese Institute of Engineers, Series E >A LOW COMPLEXITY COMPLEX QR FACTORIZATION DESIGN FOR REAL TIME MIMO SIGNAL DETECTION
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A LOW COMPLEXITY COMPLEX QR FACTORIZATION DESIGN FOR REAL TIME MIMO SIGNAL DETECTION

机译:用于实时MIMO信号检测的低复杂度复杂QR分解设计

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摘要

Complex QR factorization (CQRF) is a fundamental operation used in various MIMO signal detection algorithms. In this paper, we revise the Givens Rotation based factorization algorithm and develop an efficient computation scheme working in the real number domain. The proposed scheme can reduce the computing complexity to almost one half by exploiting the symmetric property. Based on the new scheme, a novel systolic array design featuring fully parallel and deeply pipelined processing was derived subject to the EWC 802.11n recommendation. CORDIC algorithm is employed to implement the required rotation operations with low circuit complexity. No Look-up-table (LUT) is needed in this CORDIC design to reduce the circuit complexity. Chip implementation results in TSMC 0.13μm process indicate the proposed design, bearing a gate count of 156K, is capable of performing one 4×4 CQRF in every 8 clock cycles. It also has a measured maximum clock rate of 81 MHz with 85.86mW power consumption.
机译:复杂QR分解(CQRF)是各种MIMO信号检测算法中使用的基本操作。在本文中,我们修改了基于Givens旋转的因式分解算法,并开发了一种在实数域中工作的有效计算方案。所提出的方案可以通过利用对称性将计算复杂度降低到几乎一半。基于新方案,根据EWC 802.11n的建议,推导了具有完全并行和深度流水线处理功能的新型脉动阵列设计。采用CORDIC算法以较低的电路复杂度实现所需的旋转操作。在此CORDIC设计中不需要查找表(LUT)来降低电路复杂性。台积电0.13μm工艺的芯片实现结果表明,该设计的门数为156K,能够每8个时钟周期执行一次4×4 CQRF。它的实测最大时钟速率为81 MHz,功耗为85.86mW。

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