A Novel Sense-amplifier and Plate-line Architecture for Ferroelectric Memories

摘要

We present a novel sense-amplifier for FeRAM that is about 2.5 times faster than the conventional sense-amplifier. In addition, it has truly independent sense and write-back capability and resolves the well-known bit-line capacitance imbalance issues. Moreover, thanks to separate write-back, data can be started on its path to the chip's data output buffer, irrespective of the time required to accomplish the write-back. Furthermore, a new plate-line architecture that reduces the load per plate-line compared to conventional global plate-line schemes and employs full CMOS drivers is presented. A boosted gate voltage is not required. Therefore, it is ideal for ultra-low voltage operation. For a ferroelectric memory in 0.13 um CMOS technology that employs the new sense amplifier and the new plate-line architecture a simulated read/write cycle time of <20 ns at 1.5 volt was observed.