SYNTHESIS OF HIERARCHICAL CIRCUITS OF PARALLEL PLD-BASED LOGIC CONTROL DEVICES

摘要

We discuss a method for synthesis of parallel logic control devices, based on a combination of sequential graph charts of algorithms. The circuits are constructed as multilevel hierarchical structures of microprogramming automata, implemented by register type programmable array logics. Estimates of the limiting parameters of the control devices synthesized are given. One specific feature of this method is that it analyzes the internal feedback circuits of arrays for transmission of the synchronizing signals of parallel processes.