Design of An Enhanced Double-Tail Comparator For High Speed Adc

摘要

The need for ultra low-power area efficient and high speed analog to digital converters is pushing towards the use of dynamic regenerative comparators to maximize speed and power efficiency. Double-Tail comparator is one of the high speed comparator with small chip area. It can operates efficiently even at lower suppy voltages. In this paper, an analysis on the power consumption and delay of the Double-Tail comparator will be presented. Based on the presented analysis, a new dynamic comparator is proposed? where the circuit of conventional Double-Tail comparator is modified for low-power and high performance even at low supply voltages. The proposed comparator will be designed by changing the input stage with an inverter based amplifier concept. It is shown that in the proposed Double-Tail comparator both the power consumption as well as delay time are significantly reduced compared to the conventional Double-Tail comparator. In this paper a Flash ADC is designed with proposed Inverter based Double-Tail comparator which will give low power consumption when compared to the conventional Double-Tail Comparator, The simulation will be done using Tanner tool.