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首页> 外文期刊>Вестник Московского государственного технического университета. Серия приборостроение >Schemotechnics and peculiarities of realisation of a large optoelectronic neuro-coprocessor on the base of highly efficient vector-matrix multiplier
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Schemotechnics and peculiarities of realisation of a large optoelectronic neuro-coprocessor on the base of highly efficient vector-matrix multiplier

机译:高效载体矩阵乘法器基础上实现大型光电神经协处理器的刀写技术和特点

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摘要

Principles and general peculiarities of schemotechnical realisation of optoelectronic neuro-coprocessor for PC providing emulation of one layer of arbitrary neural network (with the number of neurons up to 1000 under their full coherence), areconsidered and described within the framework of vector-matrix multiplying. Different modifications of the highly efficient vector-matrix multiplier realisation are proposed. Developed system is able to recognise reliably images with high noise levelwithin the period no more than three time constants of output photo-receiver.
机译:PC求解仿真的光电神经协处理器的智能神经 - 协处理器的原理和通用特性(在其完全相干下的神经元数量高达1000次),并在载体矩阵乘法框架内进行。 提出了高效的矢量矩阵乘数实现的不同修改。 开发系统能够识别具有高噪声级别的可靠图像,该时段不超过输出照片接收器的三个时间常数。

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