Design of low-power SAR ADCs using hybrid DACs

摘要

In the past decade, successive approximation register (SAR) analog-to-digital converter (ADC) has become a popular topology in a wide range of resolutions and sampling rates. This paper investigates methods to improve the energy-and-area efficiency of the SAR ADCs by focusing on the design of the internal digital-to-analog converter (DAC). Different hybrid resistive-capacitive DACs are studied in detail. It is shown that more than an order of magnitude improvement in energy efficiency of the DAC is achievable. The conditions for such an improvement are discussed.