Design of a wideband low-power continuous-time ∑Δ modulator in 90 nm CMOS technology

摘要

The design of a wideband low-power continuous-time (CT) sigma-delta modulator (SAM) is presented. At system level, an improved direct design method is used which allows direct design of the modulator in continuous-time domain. The modulator employs a low-latency flash quantizer to minimize excess loop delay. Digital-to-analog (DAC) trimming technique is used to correct the quantizer offset error, which permits minimum-sized transistors to be used for fast and low-power operation. The modulator is designed in 90 nm CMOS process with single 1.0-V power supply. It achieves a dynamic range (DR) of 75 dB and a signal-to-noise-and-distortion-ratio (SNDR) of 70 dB in a 25 MHz signal bandwidth with 16.4 mW power dissipation.