A novel 8-bit 20-MS/s folded residue amplification based pipelined ADC

摘要

A novel circuit is proposed for pipelining of single-slope analog-to-digital converters (ADCs). A new input-to-residue transfer function (TF), called folded residue amplification TF, is proposed for implementing this structure. The proposed structure enables the use of single-slope sub-ADCs in low-power, small-area pipelined structures. The gain of each stage is provided by current mirrors. Based on proposed structure, an 8-bit 20-MS/s fully-differential folded residue amplification based pipelined ADC is designed and simulated in a 90 nm CMOS technology. Calculated ENOB is 7.4-bit with 240 μW power consumption.