Design and simulation of a DAC-calibrated 150 MHz bandwidth continuous-time Delta Sigma modulator in 28 nm CMOS

摘要

This paper presents transistor-level design of a continuous-time delta-sigma modulator with 150 MHz bandwidth in 28 nm CMOS process with 1.4/0.85 V supply. Architectural-level design tradeoff for the high-speed and high-resolution requirement is analyzed. A stand-alone DAC calibration scheme is proposed for the linearization of the high-speed modulator. Simulation results show that the modulator achieves signal-to-noise-and-distortion ratio of 71 dB and spurious free dynamic range of 90 dB. The chip occupies 1.9 mm(2) and consumes 213 mW.