A thread partitioning algorithm in low power high-level synthesis

摘要

This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems that describe parallel behaving circuit blocks(threads) explicitly. First it focuses on a set R of local registers in a thread. It partitions a thread into two sub-threads, one of which has R and the other does not have R. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-threads. Then power reduced circuits are synthesized, with a low area overhead, compared to original circuits. Experimental results demonstrate effectiveness and efficiency of the algorithm.