Approximate Floating Point Multiplier based on Shifting Addition Using Carry Signal from Second-Highest-Bit

摘要

Approximate computing (AC) sacrifices accuracy for better hardware performance since it relaxes the requirement of exact equivalence between the specification and implementation [1], Floating point multiplier is widely used nowadays but it consumes a large amount of hardware resources. In this paper, approximate computing is applied to floating point multiplier. We separate the mantissa part. Exact multiplication is used for higher bits and a shifting addition algorithm is applied to lower bits. The addition algorithm involves bit addition and bit shifting, which is much simpler than bit multiplication. Bit shifting process uses the specific carry signal. Some bits of the mantissa are truncated with a small loss of accuracy. The result shows that the mean accuracy of the proposed floating point multiplier is 99.17% and the lowest accuracy performs as 97.15% which can be accepted by a wide range of applications. Compared with the exact floating point multiplier, the proposed work can reduce 67.65% of area, 16.64% of delay and 75.62% of power, respectively.