Clock tree synthesis for shrinking a chip design

摘要

In this report, we present a new Clock Tree Synthesis (CTS) for shrinking a chip design. It minimizes clock skew of the chip through scaling by executing the traditional CTS with two tuned parameters for the target process instead of those for the current process. Since the program and design libraries of CTS do not need to be modified at all and it is executed with the original design data, we can take the advantage of reusing all optimized scripts for CAD which have been already designed. Then, evaluation shows our CTS keeps the skew minimized regardless of shrinking the chip and has sufficient effects on reducing clock skew compared with the traditional one. Consequently, it enables us to extend the application of scaling to LSI design.