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首页> 外文期刊>電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices >A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAM's - measurement Results of Cell Characteristics and Memory Performance
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A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAM's - measurement Results of Cell Characteristics and Memory Performance

机译:在SOI(FBC)上使用一个晶体管增益单元的内存具有适用于嵌入式DRAM的性能 - 单元特性和内存性能的测量结果

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摘要

A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21μm{sup}2(7F{sup}2 with F=0.175μm) which we named the floating body transistor cell (FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.
机译:提出了一个288kbit存储器芯片,其在SOI的尺寸为0.21μm{sup} 2(具有f =0.175μm的7f {sup} 2)上的单晶元增益单元,我们被指定为浮体晶体管电池(FBC)和基本特性 公开了电池和存储器芯片性能。 通过使用直接接入测试电路测量数据“1”和数据“0”芯片中的单元晶体管的阈值电压,并且获得了96kbit阵列的故障位图。 设计用于消除由于过程和温度波动引起的细胞特性变化的影响的传感方案被验证为工作,测量随机接入时间小于100ns。 数据持有的特性证明FBC可以满足一些嵌入存储器的保留时间规范。 访问时间和数据保留时间表明,FBC具有用作未来嵌入式DRAM存储器单元的潜力。

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