A 320-ps access, 3-GHz cycle, 144-Kb SRAM macro in 90-nm CMOS technology

摘要

A 320-ps access, 3-GHz cycle, 144-Kb SRAM macro was developed in 90-nm CMOS technology. This macro adopted an all-stage reset type control signal generator and hierarchical bit line. These techniques enabled both the cycle and access speeds to be 1.7 times compared to the corresponding speeds available with 130-nm generation technology.