Power Modeling and Runtime Performance Optimization of Power Limited Many-Core Systems Based on a Dynamic Adaptive Approach

摘要

A critical challenge in future power limited chip-multiprocessors (CMPs) is controlling power consumption under the thermal design power (TDP) budget while maximizing the performance. One effective solution to this challenge is applying dynamic adaptation techniques (the ability to dynamically distribute the available power budget amongst the components on a multi/many-core CMP) at runtime. Providing next generation analytical models for future CMPs which consider the impact of power consumption of core and uncore components such as cache hierarchy and on-chip interconnect that consume significant portion of the on-chip power consumption is largely unexplored. In this article, we propose a detailed power model which is useful for future CMPs power modeling. Based on the derived power model, we propose a convex optimization-based dynamic adaptation approach which considers the impact of power consumption of core and uncore components simultaneously to improve CMPs performance under power constraint. The proposed approach determines optimal capacity and technology of each level of the cache hierarchy based on the program characteristics, optimal degree of parallelism of the mapped program, number and position of dark and active cores, and frequency/voltage of each core of a CMP in order to satisfy the power and temperature constraints. Experimental results on PARSEC, SPLASH, and Phoenix benchmarks show that the proposed method improves throughput by about 21.6% on average and energy-delay product up to 78.6%, respectively, in compared with the conventional CMP architectures with homogenous cache system.