FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

摘要

Convolution encoding and decoding (Viterbi decoding) is a powerful method for forward error detection and correction. It has been widely used in many communication systems to improve the limited capacity and code rate of the transmission channels. This algorithm is greatly employeddecoding algorithm for conventional codes. In this paper a reverse algorithm of Convolution encoder is given to implement the Viterbi Decoder with a constraint length of K = 7 and a code rate of 2/3.