Implementation of the viterbi decoder in the FPGA plays a dominant role for power and high speed mechanisms. The viterbi decoder is the most efficient decoder. It is commonly used in a wide range of communication and data storage applications. It uses trellis coded modulation (TCM) technique to find the trellis path in the circuit. Here, pre-computation techniques have been adopted for the trellis coded modulation. The main aim of this project is to integrate more number of SOC. The general solution for achieving high speed and low power has been tested with viterbi encoder and decoder and the results are implemented using Xilinx ISim synthesis tool. Implementation results shows that the adapted mechanism plays a dominant role in today?s communication system.
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