Pseudo Pipelined COordinate Rotation DIgital Computer Discrete Cosine Transform Architecture for Image Compression

摘要

Recent research in very large scale manufacturing technology faces challenge in between productivity design and Moore’s law. Much multicore architecture are having major issues in power and being the bottleneck critical problem. These issues mainly affect the digital signal processorin real time applications like image/video processing. Discrete cosine transform is mostly used in real time signal processing application. The major requirement of real time signal processing is using special purpose hardware which fulfils hardware efficiency with high throughput. Many conventionalDiscrete Cosine Transform (DCT) algorithms were proposed in order to reduce power and achieve high speed using both multiplier and multiplier-less architectures. Distributed arithmetic (DA) technique is a multiplier-less architecture having fewer throughputs because of memory access time andaccumulator requirements. In addition DA method requires large amount of ROM and area. To address these problems proposed a power efficient multiplier less DCT architecture based on Pseudo rotation CORDIC (COordinate Rotation DIgital Computer) algorithm. The Pseudo rotation CORDIC algorithmis based on pipeline principle. The two-dimensional (2-D) DCT architecture is designed using separable property where the scaling factor compensation is approximated. DCT architecture simulated and synthesized in Xilinx Virtex-6 XC6VLX240T FPGA. Results are shown in which the Pseudo rotationCORDIC algorithm outperforms other DCT algorithms with much reduced area and power.